Parasitic Extraction Research Articles

Testing the viability of poultry droppings as an option in the management of soil nematodes on <i>Capsicum annuum</i> plant

A survey to evaluate the viability of poultry droppings as a management option for the control of plant parasitic nematodes was tested on Capsicum annuum. Bell pepper monoculture farms cultivated conventionally and another with poultry droppings as fertilizer were surveyed. Soil samples were collected using a hand trowel while roots were collected by means of kitchen knife. Plant parasitic nematodes extraction was done by using sieve plate method. Nematodes were identified using the light microscope of x4 and x10 objectives, and identification was done using a pictorial key. Roots assay from the conventional far revealed a total of 175 endophytic nematodes from 10 genera while 56 nematodes from 6 genera were extracted from the farm with poultry droppings. Nematode dynamics in diversity was observed such that certain nematode genera such as Meliodogyne, Radopholus, Pratylenchus, Ditylenchus, Hoplolaimus, Rhaditis were reported in both plots. Phyto-parasitic species were predominant at the conventional farm plot whereas nematodes predatory species recorded higher populations in the farm plot with poultry droppings, an observation which depict that parasitic nematodes could be inhibited by the presence of free living species. This observation further suggests that poultry droppings can adequately fit in as a management of nematodes management if properly harmonised.

Antimicrobial and antioxidant test of several mistletoe extracts (Scurrula ferruginea (Roxb. Ex.Jack) Danser) from avocado plants

Scurrula ferruginea (Roxb. Ex. Jack) Danser is a mistletoe plant which is used by the community as a medicine for lowering blood pressure, cough medicine, diabetes, diarrhea, wounds, smallpox, skin infections, ulcers, diuretics and hypertension. This study aims to determine the antimicrobial potential, determine the Minimum Inhibitory Concentration (MIC) and Minimum Lethal Concentration (MLC) as well as determine the antioxidant activity and total polyphenols from fresh, boiled and steeped extracts of mistletoe (S. ferruginea) from avocado plants. The microbial tests used in this study were S. aureus, E. coli, and C. albicans. This study carried out in experimented methods and designed in nested pattern. The results showed that the inhibition zone of the avocado parasite extract had a significantly different effect on S. aureus and E. coli, but did not have a significantly different effect on the C. albicans test microbe. The MIC of fresh extract is true against S. aureus and E.coli which is 6.125% with 50% MLC. The optimal antioxidant value was obtained from fresh mistletoe extract with an IC50 value of 117.8 µg/ml in the medium activity category and the highest total polyphenols obtained from fresh extract was 67.80 mg. GAE/ml.

THE STUDY of SOME BIOLOGICAL ACTIVITIES of CUSCUTA CHINENSIS and ITS TWO HOSTS

Introduction: Cuscuta, (Ces as Persian name) is a parasitic plant with different biological effects and applications. The metabolic profile and effects of the Ces depend on the host on which it grows. Its main components are phenols and flavonoids. Considering the antioxidant effects of these compounds, the purpose of this research was to investigate the antioxidant activities and total phenolic and flavonoid contents of Cuscuta as well as Mellissa officinalis and Alhaji murarum as hosts.
 Methods:  Aqueous, hydroalcoholic extracts of the Cuscuta grown on two hosts were prepared separately. Hydroalcoholic extracts of host plants were also prepared. Total phenolic and flavonoid contents were evaluated using Folin- Ciocalteu reagent and aluminum chloride colorimetric assays, respectively. In order to investigate the antioxidant activity, the ability of extracts to scavenge DPPH free radical (DPPH 2, 2-(diphenyl-1-picrylhydrazyl) and their capacity to reduce iron 3+ion were measured by FRAP method.
 Results: The results showed that all the examined extracts have significant phenolic and flavonoid contents. The highest antioxidant activity was observed in hydroalcoholic extracts, which was proportional to the amount of phenolic and flavonoid contents in the extracts. In addition, the extracts of host plants were richer than the parasite extracts. The extract of Mellissa officinalis showed better effects than Alhaji murarum in all of four investigated factors.
 Conclusion: According to the findings of the present study, the hydroalcoholic extracts of the Cuscuta plants are rich in phenolic and flavonoid compounds, which may be the cause of the antioxidant activity. Of course, the compounds and effects of Cuscuta depend on the host. In future studies, the plant can be grown in different hosts.

Evaluation of Anticancer and Antioxidant Activities of Coffee Stem Parasite Extract <i>(Scurrula Ferruginea (Roxb. Ex Jack) Danser)</i> and in Silico Studies of its Isolate

Evaluation of Anticancer and Antioxidant Activities of Coffee Stem Parasite Extract <i>(Scurrula Ferruginea (Roxb. Ex Jack) Danser)</i> and in Silico Studies of its Isolate

Mitigating the Effects of Design for Manufacturability on Design Iteration Cycles in Advanced Integrated Circuit Design

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses

Recent studies in power electronic design automation have introduced various models for parasitic extraction of multichip power module layouts. However, none of these studies consider the eddy current effect in the direct-bonded-copper substrate, accounting for 40-50% error in the extraction result. This work introduces a methodology for eddy-current consideration through numerical simulation and regression modeling. The regression model utilized in the characterization process in this work is fast and memory-efficient compared to the finite element approach. This characterization process can improve the accuracy of any partial element model without sacrificing performance. Combining this characterization process and partial element approach achieves less than 10% extraction error compared to Ansys Q3D while showing a maximum speed-up of 35× and 17× more memory efficiency. This method also significantly reduces the number of elements in the extracted netlist and the complexity of loop evaluation. This method is attractive for use with optimization routines and therefore has been used successfully in a layout optimization tool.

Anthelmintic efficacy of Phlogacanthus thyrsiflorus leaf extract on juvenile and adult worms of Hymenolepis diminuta (Cestoda).

The leaves of Phlogacanthus thyrsiflorus are used as an anthelmintic remedy by the tribal communities of upper Assam in India. The present study was carried out to validate the anthelmintic credentials of this plant. Mature and larval Hymenolepis diminuta worms were exposed to varying concentration of methanolic leaf extract of plant and parasites were observed for paralysis and mortality. At the end of the experiment, worms were collected and processed for scanning electron microscopy (SEM) study to observe the effect of extract on tegument of parasite. The in vivo study was carried out in H. diminuta-rat model with 200, 400 and 800mg/kg concentrations of extract. The in vivo anthelmintic efficacy was assessed by reductions in egg per gram (EPG) and worm counts after necropsy of animals. In vitro studies revealed the earliest mortality of larval worms in 1.05 ± 0.04h by 30mg/ml concentration and of adult worms in 2.05 ± 0.08h. SEM study revealed extensive damage to the suckers, body tegument and microtriches of worms treated with 30mg/ml concentration of extract. In in-vivo studies, 800mg/kg dose of extract showed highest efficacy, with 59% and 54.25% reduction in EPG counts and worm count against juvenile worms, and 63.16% and 66.75% reduction in EPG counts and worm counts, respectively against adult worms. Although the effects were comparatively less than the reference drug, nevertheless this study reveals that P. thyrsiflorus possess anthelmintic efficacy and justify its use in traditional medicine against intestinal-worm infections.

SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs

Gate-all-around field effect transistors (FETs) are set to replace FinFETs to enable continued miniaturization of ICs in the deep nanometer regime. IMEC and IRDS roadmaps project that 3D integration of gate-all-around FETs is a key path for the IC industry beyond 2024. In this article, we present SkyBridge 2.0, an IC technology featuring high density fine-grained 3D integration of vertical gate-all-around nanowire FETs, contacts, and interconnect while also solving 3D routability. We utilize industry-standard EDA tools to develop a customized design and technology co-optimization (DTCO) flow to design and evaluate SkyBridge 2.0. This DTCO flow covers process emulation of standard cells and SRAM to enable scalable manufacturing pathway, TCAD characterization of vertical nanowire FETs to obtain IV and CV characteristics, compact modeling accurately the device behavior, RC parasitic extraction of 3D interconnects and performance, and power and area assessment using ring oscillators. The technology assessment using ring oscillators shows that SkyBridge 2.0 at the chosen design point, using 10 nm nanowires, achieves ∼18% performance and 31% energy efficiency benefits compared to 7 nm FinFET technology. Area analysis of logic cells shows up to six times density benefits versus aggressively scaled 2D-CMOS cells. In addition to logic, we architect 3D SRAM to support low-power memory designs. SkyBridge 2.0 SRAM shows ∼20% improvement in read and write static noise margin, up to  three times lower leakage current, and up to four times density benefits compared to 7 nm FinFET technology.

Carrier multiplication in perovskite solar cells with internal quantum efficiency exceeding 100%

Carrier multiplication (CM) holds great promise to break the Shockley-Queisser limit of single junction photovoltaic cells. Despite compelling spectroscopic evidence of strong CM effects in halide perovskites, studies in actual perovskite solar cells (PSCs) are lacking. Herein, we reconcile this knowledge gap using the testbed Cs0.05FA0.5MA0.45Pb0.5Sn0.5I3 system exhibiting efficient CM with a low threshold of 2Eg (~500 nm) and high efficiency of 99.4 ± 0.4%. Robust CM enables an unbiased internal quantum efficiency exceeding 110% and reaching as high as 160% in the best devices. Importantly, our findings inject fresh insights into the complex interplay of various factors (optical and parasitic absorption losses, charge recombination and extraction losses, etc.) undermining CM contributions to the overall performance. Surprisingly, CM effects may already exist in mixed Pb-Sn PSCs but are repressed by its present architecture. A comprehensive redesign of the existing device configuration is needed to leverage CM effects for next-generation PSCs.

Tracking of bifurcations and hysteresis in electrostatically actuated resonators by motion-induced current

In this work, we present an experimental technique to detect the onset of bifurcation and measure the extent of hysteresis in electrostatic MEMS. The device-under-test comprises a microcantilever beam actuated via a side electrode. The beam vibrations result in varying the resonator’s capacitance, therefore inducing a current that can be measured and used for characterization and performance analysis. The motion-induced current is measured, and its harmonics are extracted using a lock-in amplifier. Locking on the third harmonic of the induced current enables us to bypass parasitic capacitance and extract a signal directly related to the resonator motions. We show that this signal can be used to investigate the nonlinear dynamic behavior of MEMS resonators undergoing large motions. Specifically, our experiments demonstrate our technique's ability to detect various bifurcations, to track the onset of hysteresis, and to measure the hysteresis bandwidth. We also use our technique to analyze the quantitative relationships between the actuation voltage, the location of the bifurcation point, and the hysteretic bandwidth. Finally, we show that our technique can be used to generate the calibration curves for inertial MEMS sensors.

Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology

Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology

Analysis and Implementation of Controlled Semiconductor Switch for Ultra-Wideband Radar Sensor Applications.

All ultra-wideband (UWB) sensor applications require hardware designed directly for their specific application. The switching of broadband radio frequency and microwave signals is an integral part of almost every piece of high-frequency equipment, whether in commercial operation or laboratory conditions. The trend of integrating various circuit structures and systems on a chip (SoC) or in a single package (SiP) is also related to the need to design these integrated switches for various measuring devices and instruments in laboratories, paradoxically for their further development. Another possible use is switching high-frequency signals in telecommunications devices, whether mobile or fixed networks, for example, for switching signals from several antennas. Based on these requirements, a high-frequency semiconductor integrated switch with NMOS transistors was designed. With these transistors, it is possible to achieve higher integration than with bipolar ones. Even though MOSFET transistors have worse frequency characteristics, we can compensate them to some extent with the precise design of the circuit and layout of the chip. This article describes the analysis and design of a high-frequency semiconductor integrated switch for UWB applications consisting of three series-parallel switches controlled by CMOS logic signals. They are primarily intended for UWB sensor systems, e.g., when switching and configuring the antenna MIMO system or when switching calibration tools. The design of the switch was implemented in low-cost 0.35 µm SiGe BiCMOS technology with an emphasis on the smallest possible attenuation and the largest possible bandwidth and isolation. The reason for choosing this technology was also that other circuit structures of UWB systems were realized in this technology. Through the simulations, individual parameters of the circuit were simulated, the layout of the chip was also created, and the parameters of the circuit were simulated with the parasitic extraction and the inclusion of parasitic elements (post-layout simulations). Subsequently, the chip was manufactured and its parameters were measured and evaluated. Based on these measurements, the designed and fabricated UWB switch was found to have the following parameters: a supply current of 2 mA at 3.3 V, a bandwidth of 6 GHz, an insertion loss (at 1 GHz) of -2.2 dB, and isolation (at 1 GHz) of -33 dB, which satisfy the requirements for our UWB sensor applications.

Deep-Learning-Driven Random Walk Method for Capacitance Extraction

Random-walk based methods for solving Partial Differential Equations (PDEs) exhibit significant advantages and applicability to numerous domains. One of these is parasitic capacitance extraction in modern silicon technologies, where they are essentially called upon to solve a boundary-value problem. In this regime, fast and accurate calculation of the Green’s function within the transition domains of the random walk is critical for competitive performance. Silicon processes in advanced nodes introduce complex or special dielectric structures that challenge currently established methods for characterizing the Green’s function. In this paper, a novel approximation method for the Green’s function and the Green’s function gradient is presented, which leverages Group-Equivariant Convolutional Neural Networks (G-CNNs). This can accompany existing multi-tier Green’s function data pre-computation schemes. Additionally, it enables performing the crucial step of sampling according to the Green’s function without explicit calculation of the Green’s function itself. A novel end-to-end random-walk architecture is discussed which incorporates such deep neural-networks, and its utility is demonstrated though numerical experiments. The proposed scheme enjoys massive gains in terms of speed for advanced CMOS nm node setups with non-planar dielectric media, compared to a straight Finite Differences Method (FDM) solution, while maintaining good accuracy levels.

MLTDRC: Machine learning driven faster timing design rule check convergence

Timing design rule check (T-DRC) convergence follows an iterative procedure like physical design closure. On a medium-complex design, the conventional flow of T-DRC convergence requires about 14 h per iteration, which includes fill insertion, sign-off accurate standard parasitic extraction format generation, sign-off static timing analysis, engineering change order (ECO) list generation in the multi-corner multi-mode scenario, fill removal, and implementation of the ECO on the pre-fill design. The T-DRC values generated from the pre-fill stage auto-place and route tool often have a miscorrelation with the sign-off values obtained from the static timing analysis tool. Due to the correlation gap, designers prefer to wait for the ECO change list to be created by the sign-off tool at the end of each iteration rather than resolve it at the pre-fill stage in the construction tool. Hence, T-DRC convergence is a lengthy process. This paper discusses an automatic T-DRC convergence methodology driven by machine learning (ML) techniques. By anticipating the transition of the input pin of a cell and the capacitance of its output pin, the suggested methodology shortens the runtime of each iteration. Additionally, it forecasts the suitable buffer to correct the T-DRC violation in the case of buffer insertion. With almost accurate prediction of T-DRC values using the ML approach, the sign-off flow can now be bypassed for a few iterations during the timing convergence phase, resulting in fewer iterations in the T-DRC sign-off flow. The violation percentage and the desired buffer name are obtained from the ML prediction result for each violation. An automatic in-house T-DRC fixer flow is developed to correct the violating elements beforehand, saving around 12 h of runtime for each iteration. Since ML prediction can never be 100% accurate, the final timing sign-off should always be done with the sign-off tool and flow to ensure zero silicon bug. With the help of ML prediction and the T-DRC fixer methodology, T-DRC convergence is possible in fewer sign-off tool iterations, resulting in a left shift of about two weeks in the timing closure cycle on the actual project execution.

New Methodology for Parasitic Resistance Extraction and Capacitance Correction in RF AlGaN/GaN High Electron Mobility Transistors

This paper presents a novel approach to the efficient extraction of parasitic resistances in high electron mobility transistors (HEMTs). The study reveals that the gate resistance value can be accurately determined under specific forward gate bias conditions (Vg = 1.0 V), although the gate resistance value becomes unreliable beyond this threshold (Vg > 1.0 V) due to potential damage to the Schottky contact. Furthermore, by examining the characteristics of the device under a cold-FET bias condition (Vds = 0 V), a linear correlation between the gate and drain current is identified, enabling an estimation of the interdependence between the drain and source resistance using the proposed method. The estimation of parasitic pad capacitance (Cpg and Cpd) from Dambrine’s model is refined by incorporating the depletion layer capacitance on the gate side during the pinch-off condition. To validate the accuracy of the extracted parasitic capacitance and resistance values obtained from the new method, small-signal modeling is performed on a diverse range of measured devices.

Анализ влияния шин трассировки на результаты моделирования стандартных цифровых элементов по технологии КМОП 28 нм

In this paper, the influence of routing buses on the timing characteristics (rise/fall time and switching delay) of standard digital elements due to the manifestation of LDE and parasitic effects was studied. A set of specialized test structures to take into account such effects in layers from the first to the fourth metal was proposed. The test structures provide some of the possible cases of the relative position of the routing buses and the layout of the standard cell. Parasitic extraction and characterization of the resulting netlist were performed for each test structure. A set of netlists with parasitic parameters was characterized. It is shown that the average deviation of the temporal characteristics ranged from 1.8 to 3.9% compared to the original structure without routing buses. The largest relative deviation in switching delay is typical for the smallest load capacity, while the relative deviation of cell characteristics depends relatively weakly on the front value. On the basis of the study, recommendations were formulated for modifying the route of extraction of parasitic parameters of standard digital elements, taking into account the routing buses, in order to increase the accuracy of their modeling.

Care as (re)capture: Data colonialism and race during times of crisis

This article examines the role that data-driven technologies play in expanding and reasserting the legitimacy of the US racial state during times of crisis. Specifically, I examine how prison officials used a software called Verus to reinforce the perceived necessity of penal institutions during the COVID-19 pandemic. Government officials used Verus to produce narratives that (1) recast criminalized communities as dangerous and therefore disposable and (2) shielded carceral institutions from liability for systematic neglect. Ultimately, the aim of this article is to contribute to emerging critical concepts such as “data colonialism,” a term that has largely been used to describe the social and economic consequences of parasitic data extraction and monopoly control of digital infrastructure. In addition to these issues, I argue that data-driven technologies are used as vehicles for movement capture and the reproduction of prison logics that enable modes of racialized economic exploitation that extend far beyond the high-tech innovation economy.

Parasitic Parameter Extraction for Calibration Standards Using an Optimization Strategy

This article presents a novel extraction method for parasitic parameters of on-wafer calibration standards using an optimization strategy. Based on the physical models of the calibration standards, the parasitic parameters of all calibration standards can be extracted using the Bayesian optimization method with a fast calculation speed and high accuracy. Compared with the conventional thru-reflect-line (TRL) extraction method, the proposed approach can work well in systems with high crosstalk. The methodology is validated through on-wafer measurements using a ground–signal–ground (GSG) probe with low crosstalk and a ground–signal (GS) probe with high crosstalk. The proposed method shows a comparable accuracy with the TRL method in the low-crosstalk case, while it has higher accuracy in the high-crosstalk scenario.

Extraction of Interconnect Parasitic Capacitance Matrix Based on Deep Neural Network

Interconnect parasitic capacitance extraction is crucial in analyzing VLSI circuits’ delay and crosstalk. This paper uses the deep neural network (DNN) to predict the parasitic capacitance matrix of a two-dimensional pattern. To save the DNN training time, the neural network’s output includes only coupling capacitances in the matrix, and total capacitances are obtained by summing corresponding predicted coupling capacitances. In this way, we can obtain coupling and total capacitances simultaneously using a single neural network. Moreover, we introduce a mirror flip method to augment the datasets computed by the finite element method (FEM), which doubles the dataset size and reduces data preparation efforts. Then, we compare the prediction accuracy of DNN with another neural network ResNet. The result shows that DNN performs better in this case. Moreover, to verify our method’s efficiency, the total capacitances calculated from the trained DNN are compared with the network (named DNN-2) that takes the total capacitance as an extra output. The results show that the prediction accuracy of the two methods is very close, indicating that our method is reliable and can save the training workload for the total capacitance. Finally, a solving efficiency comparison shows that the average computation time of the trained DNN for one case is not more than 2% of that of FEM.

Accurate SiC MOSFET Chip Extraction Based on Parasitic Parameter Impact Compensation

With the growing use of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> in power electronic equipment, it is meaningful to extract precise typical waveforms and characteristics for device manufacture, converter design, and operating evaluation. Many solutions have been proposed to improve measurement precision by equipment and essential techniques. However, the measured object should also be accurately identified as the existing measurement result consisting of the expected gate-source voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and voltage drops on parasitic parameters between measuring points. This article, first, reveals the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> measurement deviation of TO-247-4 and TO-247-3 devices during the switching process and crosstalk, based on the equivalent circuit model and simulation waveforms. According to the clarification of the measured object, an improved <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> extraction method is proposed to eliminate this deviation. Voltage drops on parasitic parameters are compensated, with the help of high-precision equipment and the proven parasitic parameter extraction technique. Experiments are constructed to verify the analysis of measurement deviation and the availability of the proposed method. Comparison between various operating conditions emphasizes its necessity, especially in high-capacity and low-driving-resistor applications, contributing to characterization, operating condition monitoring, protection design, and measurement understanding of wide band-gap devices.